AMD Confirms Zen 6 CPUs Will Support AVX512 And These Other Instruction Sets

The idea that AMD's Zen 6 would support AVX-512 in some fashion has never really been in question, to tell the truth. With native 512-bit vector datapaths and a nearly-complete AVX-512 implementation, AMD's Zen 5 already has the strongest AVX-512 support on client systems, but it does seem like Zen 6 is poised to expand that support considerably. We know this thanks to recent patches submitted for the GNU Assembler (Gas).

Specifically, the patches plumb out a new "Znver6" target for Gas that confirms the new architecture for everything Zen 5 supports, as well as new instruction set extensions: AVX512_BMM, AVX_NE_CONVERT, AVX_IFMA, AVX_VNNI_INT8, and AVX512_FP16. Of those, only AVX512_BMM is truly novel; the rest are already supported by Intel's Granite Rapids Xeon processors. AVX512_BMM is a new set of instructions designed to accelerate bit masking operations for matrices, which offers big wins for binary neural networks.