AMD bets on rack-scale compute to boost AI efficiency 20x by 2030

With Moore's Law on its last legs and datacenter power consumption a growing concern, AMD is embarking on an ambitious new goal to boost the energy efficiency of its chips 20-fold before 2030. And it sees rack-scale architectures as a key design point to get there.

"The counterintuitive thing here… is the bigger the device, the more efficient it is," AMD SVP and Fellow Sam Naffziger tells El Reg. "But what we're getting is what used to be a whole rack of compute devices in a single package."

AMD was among the first to apply this logic to its CPUs and GPUs, embracing a chiplet architecture that enabled it to overcome reticle limits and squeeze more performance from each watt consumed.

The ultimate culmination of this philosophy was AMD's MI300 series of APUs and GPUs, which formed a dense sandwich of 3D stacked compute, I/O dies ...